In the field of high speed digital to analog conversion systems, particularly in satellite applications, there is an ongoing effort to include frequency upconversion in the digital domain by implementing higher speed digital to analog up converter circuits with integrated digital mixer circuits. However, time misalignment of digital data signals after the mixer circuit is a concern to achieving high speed upconversion system performance. The time misalignments are due in part to differences between data signal logic transitions and conversion clock transitions at the inputs of the digital mixer circuit.
Various conventional techniques attempt to reduce the time misalignments. For example, current mode logic circuit topologies may be used to reduce a portion of the time misalignments, but have the disadvantage of increasing power dissipation without significant improvement to system performance. Another conventional technique to address time misalignments may be to manually adjust physical signal paths in the digital to analog upconverter, but this step may be time consuming and may not be feasible if the digital to analog upconverter is used for different applications (e.g., frequency upconversion at different data rates).